1. Field of the Invention
The present invention relates to a sample-and-hold apparatus. More particularly, the present invention relates to a sample-and-hold apparatus that prevents output distortion caused by a charge distribution effect and an operating method thereof.
2. Description of Related Art
Usually, many different sample-and-hold apparatuses are used in electronic devices. For example, FIG. 1 is a block diagram of a conventional liquid crystal display (LCD). As an LCD panel 110 commonly has hundreds of (or even thousands of) data lines, a source driver must have the same number of sets of data channels. For a large panel, a source driver composed of thousands of sets of data channels is required for driving the display panel. Therefore, a larger chip area is required to realize the source driver, thus the cost of the source driver is very high. Thus, for reducing cost, multiple data lines must share one set of data channels.
Referring to FIG. 1, the source driver 120 has few data channels (e.g., 80 data channels). During the period of a horizontal line, each data channel is responsible for time division latching 8 digital data D, and converting the 8 digital data D into analog signals successively. Sample-and-hold apparatuses 130 synchronously sample the corresponding analog signals, and store the 8 sampling results in 8 sets of sampling channels in the sample-and-hold apparatuses 130 respectively. In addition, each of the sample-and-hold apparatuses 130 sequentially outputs the previous 8 sampling results to a corresponding demultiplexer 140. The demultiplexer 140 then switches the sampling results to the corresponding data lines on the corresponding display panel 110. Therefore, the source driver 120 needs only 80 sets of data channels to drive 640 data lines on the display panel 110 with the time division multiplex technology.
In the conventional sample-and-hold apparatus, as a read switch is disposed between a sampling capacitor and a read operational amplifier, a charge distribution effect occurs when the parasitic capacitances at the input terminals of the operational amplifier near the capacitances of the sampling capacitor. FIG. 1A is a circuit diagram of a conventional sample-and-hold apparatus. The sample-and-hold apparatus receives an input voltage Vi, and outputs a voltage Vo after sampling. The sample-and-hold apparatus includes switches 11-1 to 11-n, switches 12-1 to 12-n, sampling capacitors 13-1 to 13-n, and a sampling amplifier 14. The parasitic capacitance exists between the input terminal of the sampling amplifier 14 and the ground.
As shown in FIG. 1A, n sets of sampling channels of the conventional sample-and-hold apparatus are composed of the switches 11-1 to 11-n, the switches 12-1 to 12-n, and the sampling capacitors 13-1 to 13-n. The control sequence of the switches in FIG. 1A is as shown in FIG. 1B. When the sampling capacitor 13-(I+1) samples, the voltage value of the previous sampling capacitor 13-(I) is held (1≦I≦n), and is output by the sampling amplifier 14. Or, as shown in FIG. 1C, the data are sampled and stored in corresponding sampling capacitors sequentially, and then read out from the sampling amplifier 14 sequentially. Control signals T11-1 to T11-n control the switches 11-1 to 11-n respectively, and control signals T12-1 to T12-n control the switches 12-1 to 12-n. The conventional sample-and-hold apparatus has a serious defect, i.e., the sampled voltages held in the sampling capacitors 13-1 to 13-n will have charge redistribution due to the parasitic capacitance between the input terminal of the sampling amplifier 14 and the ground. In addition, the conventional sample-and-hold apparatus further has clock feed-through effect, charge injection effect, and other effects, thus leading to errors. Due to different input voltages, the error voltages are different, thus leading to non-linear output and the distortion of the output.
In order to reduce the voltage error, an improvement of the conventional sample-and-hold apparatus reduces the error by increasing the capacitances of the sampling capacitors 13-1 to 13-n. However, the increase of capacitances will cause the increase of the overall power consumption accordingly, reduce the speed, and increase the chip area.
FIG. 2 is a circuit diagram of another conventional sample-and-hold apparatus. The sample-and-hold apparatus receives an input voltage Vi, and outputs a voltage Vo after sampling. The sample-and-hold apparatus includes switches 21-1 to 21-n, switches 22-1 to 22-n, sampling capacitors 23-1 to 23-n, and sampling amplifiers 24-1 to 24-n. In FIG. 2, the control sequence of the switches 21-1 to 21-n is similar to the sequence of the control signals T11-i to T11-n in FIG. 1B respectively, and the control sequence of the switches 22-1 to 22-n is similar to the sequence of the control signals T12-1 to T12-n in FIG. 1B respectively. As the sampling capacitors 23-1 to 23-n are directly coupled to the sampling amplifiers 24-1 to 24-n without using the switches, each sampling channel charges the sampling capacitor in the sampling channel (one of 23-1 to 23-n) and the parasitic capacitor of the sampling amplifier (one of 24-1 to 24-n) at the same time when the input voltage Vi is sampled. Thus, the charge redistribution is prevented. However, as the read switches 22-1 to 22-n are disposed subsequent to the sampling amplifiers 24-1 to 24-n, each set of the sampling channels needs one corresponding read sampling amplifier (in FIG. 2, n sets of sampling channels are provided, so n sampling amplifiers are required). Therefore, the chip area will be increased greatly according to the conventional art.